Double Clocked FFT Core

Jun 24, 2015	This is a bug fix release. The output performance under Verilator simulation now matches FPGA performance with Vivado as the synthesizer. Further, a bug was found and corrected in the non-hardware optimized butterfly.	Gisselquist, Dan
Jun 2, 2015	Updating usage statistics with 32 point and 64 point FFT usage.	Gisselquist, Dan
Jun 2, 2015	With today's updates, the double clocked FFT core is now FPGA proven! It successfully maps to and uses DSP48's and block RAM's. I'm still collecting usage statistics to post, but it can do a 16-bit, 1024 point, forward and inverse transform within a Basys-3 development board.	Gisselquist, Dan
May 31, 2015	Still working on an FPGA proven version. This version will optimize its use of hardware multiplies and even use a lot more block RAM than the current version. I'll upload the changes as soon as ... well, as soon as it works again. Right now the new version compiles and builds, but delivers the wrong answers ...	Gisselquist, Dan
May 30, 2015	Updated the project page to reflect changes made today, but not yet propagated to SVN.	Gisselquist, Dan
May 29, 2015	Updated the project page to pre-announce some changes that are coming.	Gisselquist, Dan
Mar 13, 2015	The core now compiles under Vivado without errors. Further, a command line option to the core generator allows the core to use hardware multiplies, such as DSP48's, internal to the FFT and therefore to use fewer generic gates.	Gisselquist, Dan
Mar 8, 2015	Rounding has been added into the FFT stages for bias removal. Tests so far have shown a positive improvement, although not all of the bias has (yet) been eliminated.	Gisselquist, Dan
Mar 7, 2015	A new upload today fixes several problems with the FFT's generated by the core. If you're attempting to make this work, you will want to download the updated changes.	Gisselquist, Dan
Mar 3, 2015	The double clocked FFT now has a written specification! As an added bonus, for those who love LaTeX, the specification was written in LaTeX, and I even left the class file that was built to match the open cores specification template in the documents directory as well.	Gisselquist, Dan
Mar 3, 2015	Two items of news. First, I moved the project to the DSP section so it can stand side by side with the other FFT cores available on Open Cores. Second, although the specification isn't complete, I have placed a draft specification in the documents section that should be just about good enough for whatever someone might need. Cheers!	Gisselquist, Dan
Feb 28, 2015	This FFT now passes all of my tests via verilator, although the tests remain sparse. I've tested the 2048 sized FFT that I need and it appears to work well. Other sized FFT's are available, just run the fftgen program contained within to build them. However, the fact that the FFT now works is pretty exciting!	Gisselquist, Dan
Feb 23, 2015	Just updated the description of the project, going to look at butterfly coefficient generation next.	Gisselquist, Dan

Browse

Double Clocked FFT Core