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DDR SDRAM Controller Core

## Description

The ddr\_sdr controls read and write access of a programmable  
logic device to a single 256 Mbit memory device. The 32-bit  
wide user interface basically accepts two commands, read or  
write. The control logic initializes the memory after reset  
and issues refresh commands from time to time to ensure data  
integrity. The data width to the memory device is 16 bits  
wide and performs a double data rate operation at 100 MHz  
clock rate.  

## Status

\- Version 1.0 available


<h2 id="description">Description</h2>
<p>The ddr_sdr controls read and write access of a programmable <br />
logic device to a single 256 Mbit memory device. The 32-bit <br />
wide user interface basically accepts two commands, read or <br />
write. The control logic initializes the memory after reset <br />
and issues refresh commands from time to time to ensure data <br />
integrity. The data width to the memory device is 16 bits <br />
wide and performs a double data rate operation at 100 MHz <br />
clock rate.<br />
</p>
<h2 id="status">Status</h2>
<p>- Version 1.0 available</p>


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DDR SDRAM Controller Core

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