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Hardware implementation of Binary Fully Digital Phase Locked Loop :: Overview



Project maintainers

Details

Name: dpll-isdn
Created: Mar 30, 2011
Updated: Feb 18, 2013
SVN Updated: Jun 2, 2015
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
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Other project properties

Category:Arithmetic core
Language:Verilog
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL

References

1. Yamamoto H., Mori S. Performance of a binary quantized all digital phase-locked loop with a new class of sequential filter//IEEE Trans. – 1978. – V. Com-26, №1. – P. 35-45.

2. Cessna J.R., Levy D.M. Phase noise and transient times for a binary quantized digital phase-locked loop in which Gaussian noise//IEEE Trans. – 1972. – V. Com-20, №2. – P. 94-104.

3. Yukawa J., Mori S. A binary quantized digital phase-locked loop//IECE. – 1973. – Vol. 56-A, №12. – P. 79-85.
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