OpenCores

Educational RISC Processor

Project maintainers

Details

Name: erp
Created: Sep 17, 2004
Updated: Feb 26, 2014
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 3 reported / 0 solved
Star1you like it: star it!

Other project properties

Category:Processor
Language:Verilog
Development status:Stable
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License:

Description

An implementable and enhancable RISC Core developed in Verilog HDL, tested on Xilinx IIE Spartan FPGA.

Features

- feature1
- feature1.1
-feature1.2
-feature2

Status

-Currently present Verilog Module is implementable, and also enhancements could be made as desired
- status2