Gao, Jon

10_100_1000 Mbps tri-mode ethernet MAC

MAC_rx_FF.v  contains a number of typos using a define of
 
`MAC_TX_FF_DEPTH 

when it should be

`MAC_RX_FF_DEPTH. 

Everything is fine as long as TX and RX FIFOs are the same size.

wrong size defined for RX FIFO

sim_only.mod missing for modelsim

In the file ./sim/rtl_sim/modsim_sim/bin/vlog-rtl.list
../../../../rtl/verilog/Reg_int.v should be spelled with lower case : reg_int.v

(Important when executing under case sensitive systems as UNIX/linux.)

(But then when trying to simulate, the modelsim pli files using .dll doen't really go well together with solaris;-)

Spelling mistake vlog-rtl.list

Hi,

NCSim is not supported under windows anymore so the provided PLI ip_32W_gen/check dll are useless.
Would it be possible to get their sourcecode in order to make them working under linux/unix environement nor under modelsim ?

Regards

NCSim not supported under windows anymore

The synthesis scripts reference technology specific files that are in a /rtl/verilog/TECH/xilinx (or altera) subdirectory.  These directories do not appear in CVS????

missing subdirectories in cvs?

Hi,

can you provide us a decription of the internal functionality of ip_32W_gen/check dll's, so that i can develop a corresponding vhdl/verilog function for a protable simulation ?

Regards

New version supporting modelsim is available.

ip_32W_check/gen functionality

1.)
The core has probably some syntax errors (with Quartus II) e.g.:

-----xxxx snip xxxx------- file MAC-tx.v
//MAC_rx_flow ,
input [15:0] pause_quanta ,
input pause_quanta_val ,
);
//******************************************************************************
//internal signals
//******************************************************************************

Q2V6.0 SP1 reports:

Error (10170): Verilog HDL syntax error at MAC_tx.v(90)
near text ")"; expecting an identifier, or "input", or "output", or "inout", or "(*"
-----xxxx snip xxxx------- file MAC-tx.v

The comma just before the round bracket is for some Verilog compilers a syntax error (QuartusII ...)

2.)
______________________________________________________________________

in MAC_rx.v compiler reports:

Error (10001): Verilog HDL or VHDL error at MAC_rx.v(106): object pause_quanta declared in a list of port declarations cannot be redeclared within the module body

Error (10001): Verilog HDL or VHDL error at MAC_rx.v(107): object pause_quanta_val declared in a list of port declarations cannot be redeclared within the module body

----- snip ------
output  [15:0]  pause_quanta        ,   
output          pause_quanta_val    ,   
----- snip ------
wire    [15:0]  pause_quanta        ;   
wire            pause_quanta_val    ;
----- snip ------
These signals exist as "output" and "wire" (redeclared...), QuartusII does not like it!

Maybe other compilers are more tolerant??
A fix in that direction would be nice.

KInd regards Frank

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10_100_1000 Mbps tri-mode ethernet MAC