Field-Programmable Gate Arrays (FPGAs) are flexible and reusable high-density circuits that can be (re)configured by the designer, enabling the VLSI design/validation/ simulation cycle to be performed more quickly and cheaply. The flexibility provided by FPGAs cause a substantial performance penalty due to non-specialized circuit design and signal delay through the programmable routing resources, compared do ASIC designs but FPGAs are still 1000 times faster than circuit simulators. This core provides plural of high-speed reprogrammable logic. This FPGA has regular structure and consists of three configurable elements: Look-Up-Tables (LUTs), each with 8 inputs and 2 outputs, full 4b adders and Input-Output Cells (IOCs). It logic size is aproximately equal to 1500 Virtex LUTs. The development system offers fully automated logic placement and routing (more about P&R software can be found in FPGA P&R Software document). Every non-adder function is stored in static memory array, called LUT, during programing phase. Also connections are established to match desired schematics. Programing data should be supplied by any external data source, e.g. main memory, disk, processor built. NOTE: This version does not support multiple FPGA connection, but FPGA design can be easily adopted, connecting status registers in Input Output Logic module. There is also no tristate support. Full specification Fpga.pdf (84k). More information about the WISHBONE SoC and a full specification can be found here.
Placement and routing software is a tool, which automaticaly (or with some user help) distributes given elements, so that they match certain criteria. For FPGA (Field Programmable Gate Array) this criteria usully is limited number of FPGA resources (connections, number of programmable elements, speed of (or part of) circuit, etc). More about resources and their functionality can be found in FPGA Architecture document. Command line utility is in development, which performs mapping, placement and routing for specified architecture. Currently it supports two input file types: - Verilog, GTECH library, technology independent - EDIF, technology independent Since P&R is NP-complete problem, no optimal practical solution for large placement can be found, so we are forced to search for sub-optimal solution.
KRPAN P&R Software Beta v0.1 is now available for download, but it still needs a lot of work
KRPAN.jar (118k) (Requires Java Runtime Environment v1.2).
.jar files can be run using JRE on command line:
java -jar KRPAN.jar
Jar (code correctness) can be verified using Sun's
jarsigner command line utility. OpenCores (self published) certificate is available here
KRPAN P&R software is published under GNU GPL license, available here.
Download KRPAN P&R API Documentation (
javadoc) docs.jar (398k).
Complete KRPAN P&R Java sources sources.jar (133k).
Sample Verilog file pwm12_8s.v (30k).
Java programming language was choosed, to allow full portabillity on several platforms and faster development.
Also we conjecture that Java will become more supported and used and have more computing potential. Java console applications require 70% to 250% the speed of maximally optimized C programs to calculate same results (only Windows platform was tested, but compilers provided by Sun share same code). It is estimated, for this application, that Java would run 100% slower than matching C program.
KRPAN screenshot after routing phase:
Preliminary SW documentation is available here (PDF, 81k)
email@example.com any significant progress is made.
firstname.lastname@example.org at the same time official mailing list for FPGA project.
- 13/3/2001 MM Initial web page
- 30/3/2001 MM Added KRPAN v0.1
- 5 /4/2001 MM Modifications to architecture, spec updated
- 20/4/2001 MM first SW spec available, added screen shot