Fully Pipelined Roberts, Prewitt, Sobel, Scharr Edge Detectors

Project maintainers

KOCAOGLU, Muhammed

Details

Name: fully-pipelined-edge-detection-algorithms
Created: Jan 15, 2022
Updated: Jan 15, 2022
SVN Updated: Jan 15, 2022
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved

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Other project properties

Category:DSP core
Language:VHDL
Development status:Mature
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

The core includes Roberts, Prewitt, Scharr, and Sobel edge detector algorithms. The design is fully pipelined. The latency is 5. After 5 clocks, it produces output at each clock. The desisn is generic as well. You can use the edge detector in the top module. Only the related hardware is generated.

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The url of the svn repository is: https://opencores.org/websvn/listing/fully-pipelined-edge-detection-algorithms/fully-pipelined-edge-detection-algorithms