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The url of the svn repository is: https://opencores.org/websvn/listing/fully_pipelined_128_aes_algorithm/fully_pipelined_128_aes_algorithm
128 bit fully pipelined AES algorithm. After the pipeline gets full, it gives encrypted data at each clock. The design is verified. The results obtained in VHDL are compared with the results obtained in Matlab. The design is FPGA-proven as well.