Pipelined AES Algorithm

Project maintainers

KOCAOGLU, Muhammed

Details

Name: fully_pipelined_128_aes_algorithm
Created: Jan 2, 2022
Updated: Jan 2, 2022
SVN Updated: Jan 2, 2022
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved

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Other project properties

Category:Crypto core
Language:VHDL
Development status:Mature
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

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The url of the svn repository is: https://opencores.org/websvn/listing/fully_pipelined_128_aes_algorithm/fully_pipelined_128_aes_algorithm

128 bit fully pipelined AES algorithm. After the pipeline gets full, it gives encrypted data at each clock. The design is verified. The results obtained in VHDL are compared with the results obtained in Matlab. The design is FPGA-proven as well.