Featherweight RISC-V
Project maintainers
Details
Name: fwrisc
Created: Nov 28, 2018
Updated: Nov 30, 2018
SVN Updated: Nov 30, 2018
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 1 solved
Created: Nov 28, 2018
Updated: Nov 30, 2018
SVN Updated: Nov 30, 2018
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 1 solved
Star8you like it: star it!
Other project properties
Category:Processor
Language:Verilog
Development status:Alpha
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: Others
Language:Verilog
Development status:Alpha
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: Others
Description
FWRISC is a Featherweight RISC-V RV32I implementation. All instructions and registers are supported.
Source is hosted on GitHub: [Link](http://github.com/mballancefwrisc.git)
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