Created: Sep 25, 2001
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009
Latest version: download
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The GPIO IP core is user-programmable general-purpose I/O controller. Its use is to implement functions that are not implemented with the dedicated controllers in a system and require simple input and/or output software controlled signals.
The following lists the main features of GPIO IP core:
- Number of general-purpose I/O signals is user selectable and can be in range from 1 to 32. For more I/Os several GPIO cores can be used in parallel.
- All general-purpose I/O signals can be bi-directional (external bi-directional I/O cells are required in this case).
- All general-purpose I/O signals can be three-stated or open-drain enabled (external three-state or open-drain I/O cells are required in this case).
- General-purpose I/O signals programmed as inputs can cause interrupt to the CPU.
- General-purpose I/O signals programmed as inputs can be registered at raising edge of system clock or at user programmed edge of external clock.
- All general-purpose I/O signals are programmed as inputs at hardware reset.
- Auxiliary inputs to GPIO core to bypass outputs from RGPIO_OUT register.
- Alternative input reference clock signal from external interface.
- WISHBONE SoC Interconnection Rev. B compliant interface
More information about the WISHBONE SoC and a full specification can be found here
For further information, questions and general discussions related to the GPIO core, please visit the Cores Mailing list.
- verilog RTL and verification suite are finished (see Downloads section)
- specification document is finished (see Downloads section)
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