HIVE - a 32 bit, 8 thread, 4 register/stack hybrid, pipelined verilog soft processor core

Sep 7, 2015	Project page updated to reflect v08.06 code	Wallin, Eric
Oct 10, 2014	Added quick link to Excel-based HIVE processor simulator	Wallin, Eric
Sep 16, 2014	Hive v06.01 SV and design document updated	Wallin, Eric
Jun 17, 2014	v05.04 is now written in synthesizable SystemVerilog!	Wallin, Eric
Jun 8, 2014	sim link	Wallin, Eric
Jun 8, 2014	v05.03 news	Wallin, Eric
Jan 8, 2014	Updated description text	Wallin, Eric
Jan 6, 2014	Update to reflect v04.05	Wallin, Eric
Jul 7, 2013	Added latest code version and design document.	Wallin, Eric
Jun 25, 2013	All opcodes have been checked for correct functioning.	Wallin, Eric
Jun 23, 2013	Added design document	Wallin, Eric
Jun 23, 2013	Added description	Wallin, Eric

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