Smertenko, Eli

I2C Master Slave Core

Is there a diagram or screenshot to show control signal timing?

Diagram?

I wondered, if this file worked, or if I got an old version.
I only use the slave, and had to do some changes to get it running.

Georg

slave doesen't work

I used this vhdl-file in my project, and i had to improve the stop condition, and then it worked. If i could add an attachment to this message, then i would add the waveform captured with an oscilloscope. If you want that, then you can email me: rverstraten@opencores.org.

Also, after the acknowledge, sda changes to '0' at the same time scl changes to '0'. sda should fall slightly later. That would be neater, although i left it unchanged, and it worked.

Thanks! You saved me a lot of work!

Ruben.

Stop condition

The I2C protocole include multiple master on a Bus. it could be interresting to have a multiple master manager implemented

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I2C Master Slave Core