Semiconductor Solutions, TooMuch

I2C master/slave Core

core is not synthesizable using XST:
   - unsupported division by 3
   - logic for some FF does not match a known FF template

XST synthesis

slave accessed with a READ transfer is putting 1'bx on SDA_EN line. there is no interrupt request sent to the WB controller to request a byte for transmission after the address matched and slave entered in TX mode.

SLAVE accessed in READ putting 1'bx on SDA_EN line

when accessed as SLAVE, with a Repeated START it is not responding correctly. 
The reason for that is because the counter for the bits starts counting too early after the Repeated START.

FIX suggestion:

in file ms_core.v the internal wire bit_cnt_rst should also be '1' when (detect_start = 1).

accessed as SLAVE, with Repeated START

After initial system reset, when reading register "Status register", on the WB interface, bit number 6 (Addr_match) is read with value 1'bx but it should be 1'b0.

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I2C master/slave Core