I2S Interface

The file tx_i2s_wbd.vhd contains a bug:

This portion of the code: intstat_wr <= '1' when wb_adr_i(3 downto 0) = REG_TXINTSTAT and iwr = '1' else '0';

should read: intstat_wr <= '1' when wb_adr_i(3 downto 0) = REG_TXINTSTAT and iwr = '1' and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0'; otherwise there will be arbitrary writes to the interrupt controller when writing samples to the buffer.

Thanks! This has been fixed!