Drange, Geir

I2S Interface

## FPGA Synthesis results

Resource utilization for the I2S Interface is shown below for two popular FPGA targets. Exact numbers will depend on tool used, tool settings and target architecture.

## Receiver

**I2S Receiver**

**Altera Cyclone**

**Xilinx Spartan 3**

_Slave mode_:

DATA\_WIDTH = 32  
ADDR\_WIDTH = 5  

189MHz

267 LE's

0,512kbit ram

110MHz

160 slices

18,432kbit ram

_Master mode_:

DATA\_WIDTH = 32

ADDR\_WIDTH = 5

167MHz

299 LE's

0,512kbit ram

90MHz

183 slices

18,432kbit ram

## Transmitter

**I2S Transmitter**

**Altera Cyclone**

**Xilinx Spartan 3**

_Slave mode_:

DATA\_WIDTH = 32  
ADDR\_WIDTH = 5  

144MHz

153 LE's

0,512kbit ram

105MHz

92 slices

18,432kbit ram

_Master mode_:

DATA\_WIDTH = 32

ADDR\_WIDTH = 5

124MHz

238 LE's

0,512kbit ram

90MHz

114 slices

18,432kbit ram


<h2 id="fpga-synthesis-results">FPGA Synthesis results</h2>
<p>Resource utilization for the I2S Interface is shown below for two popular FPGA targets. Exact numbers will depend on tool used, tool settings and target architecture.</p>
<h2 id="receiver">Receiver</h2>
<p>
<div><table border="1" cellpadding="2" cellspacing="2">
<tr>
<td>
<div><b>I2S Receiver</b></div>

</td>
<td>
<div><b>Altera Cyclone</b></div>

</td>
<td>
<div><b>Xilinx Spartan 3</b></div>

</td>
</tr>
<tr>
<td>
<div><i>Slave mode</i>:</div>
DATA_WIDTH = 32<br />
ADDR_WIDTH = 5<br />

</td>
<td>
<div>189MHz</div>
<div>267 LE's</div>
<div>0,512kbit ram</div>

</td>
<td>
<div>110MHz</div>
<div>160 slices</div>
<div>18,432kbit ram</div>

</td>
</tr>
<tr>
<td>
<div><i>Master mode</i>:</div>
<div>DATA_WIDTH = 32</div>
<div>ADDR_WIDTH = 5</div>
<div> </div>

</td>
<td>
<div>167MHz</div>
<div>299 LE's</div>
<div>0,512kbit ram</div>

</td>
<td>
<div>90MHz</div>
<div>183 slices</div>
<div>18,432kbit ram</div>

</td>
</tr>
</table>
</div>

</p>
<h2 id="transmitter">Transmitter</h2>
<p>
<div><table border="1" cellpadding="2" cellspacing="2">
<tr>
<td>
<div><b>I2S Transmitter</b></div>

</td>
<td>
<div><b>Altera Cyclone</b></div>

</td>
<td>
<div><b>Xilinx Spartan 3</b></div>

</td>
</tr>
<tr>
<td>
<div><i>Slave mode</i>:</div>
DATA_WIDTH = 32<br />
ADDR_WIDTH = 5<br />

</td>
<td>
<div>144MHz</div>
<div>153 LE's</div>
<div>0,512kbit ram</div>

</td>
<td>
<div>105MHz</div>
<div>92 slices</div>
<div>18,432kbit ram</div>

</td>
</tr>
<tr>
<td>
<div><i>Master mode</i>:</div>
<div>DATA_WIDTH = 32</div>
<div>ADDR_WIDTH = 5</div>
<div> </div>

</td>
<td>
<div>124MHz</div>
<div>238 LE's</div>
<div>0,512kbit ram</div>

</td>
<td>
<div>90MHz</div>
<div>114 slices</div>
<div>18,432kbit ram</div>

</td>
</tr>
</table>
</div>

</p>


I2S Receiver	Altera Cyclone	Xilinx Spartan 3
Slave mode: DATA_WIDTH = 32 ADDR_WIDTH = 5	189MHz 267 LE's 0,512kbit ram	110MHz 160 slices 18,432kbit ram
Master mode: DATA_WIDTH = 32 ADDR_WIDTH = 5	167MHz 299 LE's 0,512kbit ram	90MHz 183 slices 18,432kbit ram

I2S Transmitter	Altera Cyclone	Xilinx Spartan 3
Slave mode: DATA_WIDTH = 32 ADDR_WIDTH = 5	144MHz 153 LE's 0,512kbit ram	105MHz 92 slices 18,432kbit ram
Master mode: DATA_WIDTH = 32 ADDR_WIDTH = 5	124MHz 238 LE's 0,512kbit ram	90MHz 114 slices 18,432kbit ram

Browse

I2S Interface

FPGA Synthesis results

Receiver

Transmitter