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Details

Name: i2s_interface
Created: Jul 28, 2004
Updated: Jan 31, 2019
SVN Updated: Jul 30, 2016
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 3 reported / 2 solved
Star6you like it: star it!

Other project properties

Category:Communication controller
Language:VHDL
Development status:Stable
Additional info:Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: GPL

Features

- Separate transmitter and receiver.
- Operates in either slave or master mode.
- Configurable sample buffer size.
- Supports 16bit to 32bit resolution.
- Supports 16bit and 32bit Wishbone data bus.
- Interrupt capability.

Description

I2S is an industry standard (invented by Philips) 3-wire interface for streaming stereo audio between devices. Typical applications include digital audio transfer between a CPU/DSP and a DAC/ADC. The I2S core allows a Wishbone master to stream stereo audio to and from I2S capable devices.

Status

- Core is complete and released.