# Integer Square Root

## Details

Name: integer_square_root
Created: Oct 12, 2022
Updated: Oct 12, 2022
SVN Updated: Oct 13, 2022
SVN: Browse
Statistics: View
Bugs: 0 reported / 0 solved
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## Other project properties

Category:Arithmetic core
Language:Verilog
Development status:Stable
WishBone compliant: No
WishBone version: n/a

# Integer Square Root

## Algorithm

procedure ISR(value)
for i<-31 to 0 do
proposed_solution[i]<-1
if proposed_solution^2 > value then
proposed_solution[i]<-0
end if
end for
end procedure

## Specification

• If reset is asserted during a rising clock edge (synchronous reset), the value signal is to be stored.
• If reset is asserted part way through a computation, the result of that computation is discarded and a new value is latched into the module.
• When the module has finished computing the answer, the output is placed on the result line and done line is raised on the same cycle.
• It must not take more than 600 clock cycles to compute a result (from the last clock that reset is asserted to the first clock that done is asserted.)

## ISR State Machine

Computing: $\sqrt{\mathtt{value}}$

• On a reset

• guess initialized to 32'h8000_0000
• value is clocked into a register
• guess gets the next bit set each time we cycle through the FSM again

• Square guess (multiply it with itself)

• Wait until the multiplier raises its done
• if guess <= value

• Keep the current bit
• else

• Clear the current bit
• Move to the next bit

• After the last bit, raise done