Created: Oct 12, 2022
Updated: Oct 12, 2022
SVN Updated: Oct 13, 2022
Latest version: download
(might take a bit to start...)
0 reported / 0 solved
Integer Square Root
for i<-31 to 0 do
if proposed_solution^2 > value then
- If reset is asserted during a rising clock edge (synchronous reset), the value signal is to be stored.
- If reset is asserted part way through a computation, the result of that computation is discarded and a new value is latched into the module.
- When the module has finished computing the answer, the output is placed on the result line and done line is raised on the same cycle.
- It must not take more than 600 clock cycles to compute a result (from the last
clock that reset is asserted to the first clock that done is asserted.)
ISR State Machine
On a reset
- guess initialized to
value is clocked into a register
guess gets the next bit set each time we cycle through the FSM again
guess (multiply it with itself)
- Wait until the multiplier raises its done
Move to the next bit
After the last bit, raise