OpenCores

LCD to HDMI output IP :: Overview

Project maintainers

Details

Name: lcd_to_hdmi_output_ip
Created: Sep 1, 2018
Updated: Aug 2, 2019
SVN Updated: Aug 2, 2019
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 1 solved
Star0you like it: star it!

Other project properties

Category:Video controller
Language:Verilog
Development status:Stable
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

This is an LCD to HDMI converter that is tested on NexusVideo board from DIGILENT.
Is a generic IP that do not necesitate any setup, only take the signals from LCD IP and serialize them acording to HDMI protocol.
I provide some default timing setups of different display resolutions in the LCD IP.

I provide only a link to the original GITLAB project repository for a more easy update.
From here you can download the HDMI IP: https://git.morgothdisk.com/VERILOG/VERILOG-UTIL-IP/tree/master/interfacehdmi_out
From here you can download the LCD IP: https://git.morgothdisk.com/VERILOG/VERILOG-UTIL-IP/tree/master/interfacelcd
Here https://git.morgothdisk.com/VERILOG/VERILOG-UTIL-IP/tree/masterxmega_core is the simulation top file and here https://git.morgothdisk.com/VERILOGVERILOG-XMEGA-CORE-IP-TST is the implementation top file for NexusVideo board from DIGILENT.

Note that the source clock for the HDMI IP is 5x the pixel clock and need to be an 50/50% dutty cycle, and the pioxel clock used to drive the LCD IP is created by HDMI IP.