4004 CPU and MCS-4 family chips

NOTE: DO NOT USE THE DOWNLOAD LINK!

The "Latest version download" link does not work! It returns a tar archive from 2019, which is woefully out of date. This is supposed to be automatically generated by OpenCores, and I have no way to update the tarball. I've written to the OpenCores admins but have not received any sort of reply.

Instead of using the "download" link, use Subversion to download the repository. This still works reliably.

Description

The Intel 4004 was the first commercially-available single-chip CPU. Developed by Intel in 1969 for the Busicom company for use in the Busicom 141-PF calculator, and made commercially available for other uses in November 1971, the 4004 CPU and the other MCS-4 family chips were used in embedded applications into the mid-1980s.

This project is a translation of the pMOS, dynamic-logic MCS-4 chip set design into static-logic, functional Verilog that can be synthesized for many FPGA families. The implementation intentionally uses the net naming convention found in the 400x simulator available from the 50th Anniversary website (http://www.4004.com). Support is provided for the 4004 CPU, the 4001 ROM, 4002 RAM, and 4003 Shift Register chips.

Components from this project can be used to synthesize a complete, working, cycle-accurate, MCS-4 system in an FPGA.

A somewhat rambling blog describing this project, and companion project to implement the 4004 CPU using discrete components, can be found here: http://insanity4004.blogspot.com

License

Intel has licensed the use of the 4004 CPU schematics, chip mask images, and other documentation under a non-commercial license. This license was originally found at the following URL, but does not appear to be accessible anymore: http://www.intel.com/museum/4004ipnclicense.htm

Intel provided written confirmation to use other MCS-4 related materials in this work and publish non-commercially the recreated source materials of 4001 ROM, 4002 RAM and 4003 schematics and 4001 layout under the Creative Commons "By-attribution, Non-Commercial, Share-Alike" (BY-NC-SA) license as described here: http://creativecommons.org/licenses/by-nc-sa/3.0/legalcode

Since this project is derived from the schematics and other documentation licensed above, it necessarily carries the same non-commercial license grants and restrictions. This is not public domain material.

Current Status

April 3rd, 2022:

One latch in the Instruction Decoder module has been replaced with a clocked flip-flop to eliminate a synthesis warning.

December 2nd, 2021:

The Verilog source directory has been restructured to include implementations of all four basic MCS-4 family chips:

• 4001 ROM and 4-bit Input/Output port
• 4002 RAM and 4-bit Output port
• 4003 10-bit Shift Register
• 4004 Central Processing Unit

All known bugs in the 4004 CPU have been corrected. The Busicom 141-PF calculator software appears to run without errors in a Spartan 6 FPGA, using a custom PCB to replace the stock PCB in a Canon P170-DH calculator.

May 6, 2020:

This project is not dead, just on hiatus while I (slowly) worked on a re-creation in hardware. I've updated this project with several bugfixes to the Verilog source code for the i4004 CPU, which fix issues with conditional jumps, the ALU, and the FIM instruction. There are still a few known, unresolved bugs, but it now runs most of the sample program included in the i400x analyzer (see the 4004 50th Anniversary site for links). More fixes to come.

Nov 12, 2012:

At long last, some Verilog source code! I've uploaded the core modules that make up the 4004 CPU. Test bench code and modules that make up the 4001 ROM will be uploaded in the near future.

Sep 24, 2012:

Although I've listed the project as being in the "planning" state, the 4004 CPU is fully coded and runs simple test programs in simulation. The ROM portion of the 4001 is mostly coded and sufficiently functional to support the 4004 CPU testing; the I/O portion is partly coded and totally untested.

Verilog source code will be posted after I've done some clean-up to align it more closely with the OpenCores HDL modeling guidelines and include appropriate license info in the file comments.