Memory Controller IP Core

If we don't deassert CYC signal between reads form different memory (for example FLASH and SDRAM), FIFO won't work right. We can change line "assign re = wb_ack_o & wb_read_go;" in file "mc_dp.v" to "assign re = ( (mem_type == MC_MEM_TYPE_SDRAM) | (mem_type ==MC_MEM_TYPE_SRAM) ) & wb_ack_o & wb_read_go;" Now we write in FIFO only when we use SDRAM or SRAM