Usselmann, Rudolf

Memory Controller IP Core

When I write one byte into SDRAM, memory controller sets all 4 "mc_dqm" signals to '0' (for byte, there should be 3 "mc_dqm" signals set to '1' and only one to '0'). Possible solution: in file "mc_mem_if.v" change line 252 & 257 from "always @(posedge clk)" to "always @(posedge mc_clk)". I don't use parity bits and WB clock ("clk") is twice as fast as SDRAM's clock (mc_clk).

bugreport - writing to SDRAM

writing byte into SDRAM

If there is no other WB cycles then these which writes into memory controller's registers, initialization of SDRAM's mode register fails. Replacing "if((cs_le_d | rf_we) & wb_cyc_i & wb_stb_i)" (line 424 in "mc_rf.v") with "if(cs_le_d | rf_we)" should solve the problem.

initializing SDRAM's mode register

If we don't deassert CYC signal between reads form different memory (for example FLASH and SDRAM), FIFO won't work right. We can change line "assign re = wb_ack_o & wb_read_go;" in file "mc_dp.v" to "assign re = ( (mem_type == `MC_MEM_TYPE_SDRAM) | (mem_type == `MC_MEM_TYPE_SRAM)  ) & wb_ack_o & wb_read_go;"
Now we write in FIFO only when we use SDRAM or SRAM

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Memory Controller IP Core