OpenCores

Memory Controller IP Core :: Overview



Project maintainers

Details

Name: mem_ctrl
Created: Sep 25, 2001
Updated: Jun 10, 2018
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 6 reported / 0 solved
Star2you like it: star it!

Other project properties

Category:System controller
Language:Verilog
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License:

Description

This is a advanced Memory Controller intended for embedded applications. Some of the features are:

- SDRAM, SSRAM, FLASH, ROM and many other devices supported
- 8 Chip selects, each uniquely programmable
- Flexible timing to accommodate a variety of memory devices
- Burst transfers and burst termination
- Performance optimization by leaving active rows open
- Default boot sequence support
- Dynamic bus sizing for reading from Async. Devices
- Byte parity Generation and Checking
- Multi Master memory bus support
- Industry standard WISHBONE SoC host interface
- Up to 8 * 128 Mbyte memory size
- Supports Power Down Mode

Status

- May 2002, The core has been verified in hardware. This project is now completed.
- 8/2/2001 I have fixed various bugs and made many small changes and am still trying to improve and debug the memory controller further.
- New Directory Structure ! We have agreed on a common directory structure at OpenCores.
- I will post a message to cores@opencores.org each time I have an update

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