Memory Controller IP Core

When I write one byte into SDRAM, memory controller sets all 4 "mc_dqm" signals to '0' (for byte, there should be 3 "mc_dqm" signals set to '1' and only one to '0'). Possible solution: in file "mc_mem_if.v" change line 252 & 257 from "always @(posedge clk)" to "always @(posedge mc_clk)". I don't use parity bits and WB clock ("clk") is twice as fast as SDRAM's clock (mc_clk).