Hi,
I'm a newbie and trying to port MinSoC to De2-115 board from Altera for a MSc project.
When we try to synthesize the design using Altera QSys/SoPC Builder, we get a syntax error in the minsoc_onchip_ram.v module (at line 122) although syntactically there's nothing wrong. We've already included the minsoc_defines.v file.
Can anyone enlighten us on where we're going wrong?
Regards, AR