Ayers, Grant

MIPS32 Release 1

When the following code is executed, it seems to ignore the JALR insn.  On the simulator (iSim), it appeared to stall on the insn at 5c0, at the same time it is loading the value into register v0, no doubt because it's waiting for v0 to become valid.  The stall lasts for two memory cycles (fetches the 5c0 insn three times), then executes the J insn at 5c4:

     5b0:       02112023        subu    a0,s0,s1
     5b4:       8c420000        lw      v0,0(v0)
     5b8:       00042083        sra     a0,a0,0x2
     5bc:       0040f809        jalr    v0
     5c0:       02202821        move    a1,s1
     5c4:       08000178        j       5e0 <CommandLoop+0x1e4>
     5c8:       3c040000        lui     a0,0x0

Sorry I can't provide more info than that.  I can't easily ship you any code.  I am using your standalone CPU with both the I & D buses connected to a dual port RAM crafted from the Xilinx block RAM, running on a Spartan-6.


Your CPU seems well written, and fairly solid, other than this problem.  It was easy to drop into my project, taking only an hour or two.  Thanks!!!


Neil.

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MIPS32 Release 1