This is a soft processor core written in verilog-2001 with five pipeline stages which supports almost MIPSI instructions. MIPS789 supports gcc-elf-mips tools provided by Steve Rhords, author of plasma.In fact, this core is designed based on this complier. I’ve tested it by using a lot of C programs in a CYCLONE device EP1C6Q240 at 50MHZ frequence and it worked so well. By calculation, its CPI (cycle per instruction) is about 1.1 when run common programs.
- Five stage
- IF&ID: instructions fetch /decode.
- RF: register fetch /generate next pc (branch included).
- EXEC: execute instruction.
- DMEM: read/write data from/to data memory or device.
- WB: result write back to register bank.
- supporting interrupt by using a special way.
- dynamic IRQ address, which means you can redefine the IRQ address by point of C programs.
- using “MFC0 $RX,$RX” to save the Saved PC to register $RX.
- using “MTC0 $ZERO,$ZERO”to return from an interrupt.
- WELL TESTED
- Tested running all instructions that are implemented generated by assembler.
- Tested and running correctly at 50MHz in cyclone device EP1C6Q240 -8.
- Tested running large blocks of compiled C code.
- Only support big endian.
- DO NOT SUPPORT normal COP0 currently.
- SWL, SWR, LWL and LWR are not implemented.
I have no idea if implementing this core will or will not violate
patents, copyrights or cause any other type of lawsuits.
I provide this core "as is", without any warranties. If you decide to
build this core, you are responsible for any legal resolutions, such
as patents and copyrights, and perhaps others ....
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DESCRIPTION: structure of MIPS789
DESCRIPTION: Calculating PI with 2200 digitals (about 5second @50MHZ)