MIPS_enhanced
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Details
Name: mips_enhanced
Created: Nov 27, 2010
Updated: Apr 10, 2011
SVN Updated: Apr 9, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Nov 27, 2010
Updated: Apr 10, 2011
SVN Updated: Apr 9, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star2you like it: star it!
Other project properties
Category:Processor
Language:Verilog & VHDL
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog & VHDL
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
This project is based on MIPS789 opencores project.We used MIPS789 core and added the cache infrastracture and AMBA bus from LEON3.The final core executes MIPS I instructions.It is downloaded on a Spartan3 fpga(gr-xc3s-1500).In order to test it we used the Leon3 Testbench.
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