OpenRV64
Project maintainers
Details
Name: openrv64
Created: Jul 24, 2026
Updated: Aug 6, 2026
SVN: No files checked in
Bugs: 0 reported / 0 solved
Created: Jul 24, 2026
Updated: Aug 6, 2026
SVN: No files checked in
Bugs: 0 reported / 0 solved
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Other project properties
Category:Processor
Language:Verilog
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: CERN-OHL2-P
Language:Verilog
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: CERN-OHL2-P
Description
Currently hosted at https://github.com/bbbill42/openrv64
Boots linux with cores, with simulated ddr3 controller, verilated.
Currently merging riscv64-df extension.
Major issues are PD in terms of area and timing, more latches need to be inferred to srams.
Having http 500 error trying to add svn key, any help would be appreciated.
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