CPU passes simple tests. Verification is not complete.
This is a new implementation of the OpenRisc 1000 architecture in the Confluence language.
- OpenRisc 1000 32-bit CPU
- ORBIS32-I instructions implemented
- Exception handling partially implemented
- C test harness runs S-record programs
- Cache
- Not implemented
- MMU
- not implemented
- Other stuff
- not implemented
16 June 04 Upgraded to Confluence 0.9.0