OpenRISC 1000 (old)
News
| Aug 31, 2018 | OC-team: changed category of the old OpenRISC 1000 processor core | Admin, OpenCores |
| Mar 9, 2009 | Changes commited to CVS | Bennett, Jeremy |
| Mar 2, 2009 | Or1ksim 0.3.0 release is now available. This is the recommended, stable, version of Or1ksim. Source code, user guide and internal documentation are all available on the <a href="http://www.opencores.org/pdownloads.cgi/list/or1k">download</a> page. | Bennett, Jeremy |
| Mar 2, 2009 | Changes commited to CVS | Bennett, Jeremy |
| Mar 2, 2009 | GDB 6.8 for OpenRISC 1000, release 2.1 patch file is now available for <a href="http://www.opencores.org/projects.cgi/web/or1k/or32-gdb-6.8-patch-2.1.bz2">download</a>. This fixes some type casting requirements so it will compile with GCC 4.1.3 under Ubuntu Linux. Thanks to Sigma HH for the patches | Bennett, Jeremy |
| Mar 2, 2009 | Changes commited to CVS | Bennett, Jeremy |
| Feb 24, 2009 | Or1ksim 0.3.0 release candidate 3 now available. Source code, user guide and internal documentation all available on the <a href="http://www.opencores.org/pdownloads.cgi/list/or1k">download page</a>. This release fixes all the critical outstanding bugs. It is intended to move to full release 0.3.0 by the end of February 2009. | Bennett, Jeremy |
| Feb 21, 2009 | Icarus Verilog simulation models and Verilator cycle accurate SystemC models of ORPSoC now available in CVS at <a href="http://www.opencores.org/cvsweb.shtml/or1k/orpsoc-models/">or1k/orpsoc_models</a> or as a compressed tar file for download at <a href="http://www.opencores.org/download.cgi?rjumpto=2zb.rat.0.1-sledom-cospro/k1ro/bew/igc.stcejorp/">www.opencores.org/download.cgi?rjumpto=2zb.rat.0.1-sledom-cospro/k1ro/bew/igc.stcejorp</a> | Bennett, Jeremy |
| Feb 21, 2009 | Changes commited to CVS | Bennett, Jeremy |
| Jan 16, 2009 | Xiang Li and Lin Zuo, master students of the SoC program of KTH, Sweden have developed a general purpose embedded platform which uses the OpenRISC OR1200 processor as the CPU. For more information see the <a href="http://www.opencores.org/projects.cgi/web/or1k/orpsoc">ORPSoC page</a>. | Bennett, Jeremy |
| Nov 11, 2008 | GDB 6.8 issue 2 now available as a source code patch for the standard GDB 6.8 distribution <a href="http://www.opencores.org/projects.cgi/web/or1k/or32-gdb-6.8-patch-2.0.bz2">here</a>. This version supports the GDB <em>Remote Serial Protocol</em> and complements the release of Or1ksim 0.3.0rc2. | Bennett, Jeremy |
| Nov 11, 2008 | Changes commited to CVS | Bennett, Jeremy |
| Nov 11, 2008 | Or1ksim 0.3.0 release candidate 2 now available for download <a href="http://www.opencores.org/projects.cgi/web/or1k/or1ksim-0.3.0rc2.tar.bz2">here</a>. <em>This now supports the GDB Remote Serial Protocol</em>. You are encouraged to give this a trial and report any issues to the OpenRISC mailing list. Objective remains a stable release before the end of the year. | Bennett, Jeremy |
| Nov 11, 2008 | Changes commited to CVS | Bennett, Jeremy |
| Oct 12, 2008 | Or1ksim 0.3.0 release candidate 1 now available for download <a href="http://www.opencores.org/projects.cgi/web/or1k/or1ksim-0.3.0rc1.tar.bz2">here</a>. You are encouraged to give this a trial and report any issues to the OpenRISC mailing list. Objective is a stable release before the end of the year. | Bennett, Jeremy |
| Oct 12, 2008 | Changes commited to CVS | Bennett, Jeremy |
| Aug 31, 2008 | The source files and convenience patches for GDB 6.8 for the OpenRISC 1000 have been committed to CVS. Feedback via the OpenRISC mailing list and bug reports via the tracker are encouraged. | Bennett, Jeremy |
| Aug 31, 2008 | Changes commited to CVS | Bennett, Jeremy |
| May 14, 2008 | We are currently working on updating the OR1200 and its toolchain. More information will be presented shortly. | Erlandsson, Marcus |
| May 26, 2006 | Changes commited to CVS | lampret |
| Mar 3, 2006 | Vivace Semiconductor's roadmap, unveiled at a venture capital event in San Francisco, multimedia chips that will run Linux 2.6 on a "Vivid Media" processor that integrates an OpenRISC 1200 core with a collection of engines allowing multiple media functions to be executed on a single silicon die. | lampret |
| Jan 22, 2006 | Changes commited to CVS | Castillo Villar, Javier |
| Dec 13, 2004 | OpenRisc 1200 on a Celoxica RC203 board full source code imported to CVS | Castillo Villar, Javier |
| Oct 21, 2004 | Changes commited to CVS | phoenix |
| Aug 29, 2004 | OpenRISC 1200 implementation in single-mask <a href="http://www.viasic.com">ViaMask</a> Structured ASIC. A good alternative to FPGAs because you get more MHz and a unit price is much lower. And a good alternative to standard cell implementations because in the NRE you can save $1mio and turn around time is much shorter. <a href="http://www.opencores.org/projects.cgi/web/or1k/OR1K_ViASIC.pdf">More information</a>. | lampret |
| Jul 22, 2004 | Changes commited to CVS | lampret |
| Apr 5, 2004 | OR1200 branch_qmem got merged into OR1200 main source tree. Developments done in last 9 months are available as default (HEAD) revision and tagged as rel_27. | lampret |
| Apr 5, 2004 | Changes commited to CVS | Menart, Jure |
| Mar 26, 2004 | Between Apr 3rd and Apr 5th 2004 in San Jose, CA it is possible to see openrisc chip running Linux and a web server. <a href="http://www.opencores.org/projects.cgi/web/or1k/silicon">More information</a>. | lampret |
| Mar 26, 2004 | Changes commited to CVS | phoenix |
| Mar 18, 2004 | <a href="http://emsys.denayer.wenk.be/?proj=empro&page=intro">Tutorials</a> on the OpenRISC implementation on Xilinx and Altera FPGA boards. Very useful for beginners, a must read for everyone wanting to implement OpenRISC based system on a FPGA for the first time. Also features tutorial how to build the OpenRISC GNU toolchain. Credits go to <a href="http://emsys.denayer.wenk.be">Resarch Group Digital Techniques, Hogeschool voor Wetenschap & Kunst</a>. | lampret |
| Dec 2, 2003 | <a href="/projects.cgi/web/or1k/silicon">More information</a> on the Flextronics Semiconductor OR1200 chip. Live demos available in California between Dec 8th and Dec 15th. | |
| Aug 29, 2003 | <a href="http://www.flextronicssemi.com">Flextronics Semiconductor</a> built a SoC with OR1200, Ethernet 10/100 MAC, PCI 32 33/66, UART16550 and memory interface. Pictures of the chip from <a href="DSCN0019.JPG">top</a> and <a href="DSCN0025.JPG">bottom</a> side. More information will be available later. | |
| Jun 14, 2003 | How is California based company Rosum successfully using OR1200 in their positioning system SoC ASIC. <a href="/projects.cgi/web/or1k/ROSUM.pdf">Success story</a>. | |
| Jun 4, 2003 | Swedish magazine Elektroniktidningen published two articles about OpenCores and OpenRISC. <a href="http://www.elektroniktidningen.se/uploaded/template/asp/eltmall.asp?version=9378">Article 1</a> and <a href="http://www.elektroniktidningen.se/uploaded/template/asp/eltmall.asp?version=9377">Article 2</a>. | |
| Apr 15, 2003 | GNU toolchain and DDD are now also available for MS Windows/Cygwin environment. To download Cygwin package, go to GNU Toolchain port page. | |
| Mar 20, 2003 | How Swedish company VOXI AB successfully used OR1200 in their speech recognition system. <a href="/projects.cgi/web/or1k/voxi_success_story.pdf">Success story</a>. | |
| Dec 15, 2002 | EE Times <a href="http://www.eet.com/in_focus/embedded_systems/OEG20021213S0029">In Focus article</a> about OR1200 based SoC and embedded Linux. | |
| Dec 9, 2002 | New web section has been added, <a href="ORPsoc">ORPsoc</a>, with some nice pictures. | |
| Dec 9, 2002 | OR1200 RTL now also (optionally, disabled by default) supports WISHBONE B3 specification. | |
| Nov 12, 2002 | If you have 5 minutes, gives us some feedback by completing the <a href="/projects.cgi/web/or1k/survey">OpenRISC survey</a>. | |
| Oct 30, 2002 | Support for BIST has been added via special BIST scan chain. Right now special BIST wrapper needs to be used, at the moment this is only supported for Virtual Silicon RAMs. | |
| Sep 8, 2002 | Optional l.addc/l.addic and l.div/l.divu instructions have been added to OR1200 RTL. At the time of writing this l.addc/l.addic are not generated by or32 C compiler, but l.div/l.divu are. However if you want to use l.div/l.divu you need to install the latest or32 binutils because encoding of l.div/l.divu changed. | |
| Sep 2, 2002 | The OR1200 IP core has been chosen by <a href="http://www.flextronicssemi.com">Flextronics Semiconductor</a>, proven in FPGA technology and integrated into a Flextronics' design. Flextronics can offer commercial design services to companies that want to use this IP in their products - for more information fill out this <a href="http://www.opencores.org/cvsget.cgi?do_download=questionnaire">questionnaire</a>. | |
| Aug 22, 2002 | OR1200 RTL now has a configurable store buffer that speeds store instructions. It has been tested in orp_soc environment. Typical increase in performance is 20%. | |
| Aug 19, 2002 | uClinux is now compliant with ORP architecture. | |
| Aug 18, 2002 | Explanation of ORP has been added under ORPmon. | |
| Aug 16, 2002 | or1ksim/testbench is now completely functional (you can do 'make check' and it shouldn't fail). Test cases in testbench are now ORP compliant. | |
| Aug 16, 2002 | ATS has been greatly enhanced. Now there are two targets: or32-uclinux and or32-rtems. First with uClibc and second with newlib. Also uClinux is now built and simulated. Additionally information about last working toolchain/OS are provided (beside status of the current software in the CVS). ATS scripts are also provided. | |
| Aug 2, 2002 | Today we started news section. For start ATS is back online. In the future more items will be added to ATS. |
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