OpenRISC 1000 (old)

Overview

ORPSoC is the OpenRISC Reference Platform System-on-Chip. It follows ORP definition for memory and interrupt mapping peripherals and it can be used by developers of SoC as a starting point. ORPSoC is available from OpenCores SVN under module hierarchy or1k/orp/orp_soc. Instructions for downloading from SVN are here. ORPSoC has several software packages included:

OR1200 regression test cases
uClinux port
ORPmon

ORPSoC uses several IP cores and they are automatically updated when corresponding IP core is updated in its original CVS location (via hidden cvs links):

OR1200 processor
Ethernet MAC 10/100
UART 16550
SRAM/Flash interface
Audio interface
PS/2 interface
Simple VGA interface
JTAG debug interface

All IP cores are optimized to fit Xess XSV800 or Flextronics Semiconductor development boards. This way ORPSoC is not only simulation environment, but also can be downloaded to an FPGA board and software packages can be ran on real hardware. We are working on additional demo apps, most will be for Flextronics board. For Xess XSV800 board you can only download some precompiled demo apps. Some demos could also be used with the XSV300 board, but would have to be synthesized/implemented again for the XSV300 board. If you have an idea for a cool demo app, let us know. Such as a simple web server or something similar. And if you are willing to help, even better. Send us an email to the forum.

OpenRisc Reference Platform, ORP

OpenRISC Reference Platform (ORP) is a definition of an OpenRISC based system. It defines how address space (memory map) is organized, how interrupts are allocated by peripheral devices, much like CHRP and PReP define PowerPC systems. Right now only very simple definition is available.

An OpenRISC based system is either ORP compliant or not. The whole purpose of ORP is:

to have common OpenRISC platform that can share software
to allow easy creation of new OpenRISC based SoCs with short system verification time (you can reuse system level test cases, see this log file)

Examples of ORP compliant components:

orpmon is an example of software that runs on all ORP compliant systems without the need to modify it. See orpmon page for more information.
orp_soc is an example of reference system-on-chip compliant with ORP definition. See orp_soc page for more information.

Flextronics SoC

Flextronics Semiconductor is making a test chip of ORP compliant SoC (not ORPsoc available from the CVS). Flextronics SoC is being manufactured using 0.18um 6LM technology. Design is pad limited, with staggered 40um pads and special PCI 3.3V pads. Gate count is 150 K gates with 17 hard macros. The SoC consists of several OpenCores IP cores: - OpenRISC 1200 32-bit RISC Processor - Ethernet 10/100 MAC - 16550 compatible UART - Memory Controller (SDRAM, FLASH, SRAM, DPRAM) - 32-bit 33/66 MHz PCI - General Purpose IO (GPIO) - Development/Debug Interface - Traffic COP (Core interconnection)

uClinux/OR32 Demo App on Flextronics FPGA Development board

uClinux booting on ORPsoc, implemented on Flextronics Semiconductor FPGA Development board. uClinux console is running on VGA monitor, input is via PS/2 keyboard. In addition a camera interface was implemented to connect an external CMOS camera. Damjan L. is taking a picture with his digital camera, while Miha D. is holding external CMOS camera.
Almost full screen (NTSC size) real-time movie player implemented on Flextronics Semiconductor FPGA Development board. It plays Matrix Movie video and audio. Movie is stored in on-board flash and real-time decompressed on ORP compliant SoC (not ORPsoc) at speed of 25MHz and with no HW accelerations! This demo runs on uClinux and shows the performance of OR1k.
uClinux and MicroWindows/NanoX running on ORPsoc, implemented on Flextronics Semiconductor FPGA Development board. Snapshot of the VGA monitor running a game.
ORPmon serial console seen on a host computer. Console shows how ORPmon (codenamed Bender monitor) is being used to debug Ethernet MAC 10/100 IP core. The whole target ORPsoc is running on Flextronics Semiconductor FPGA Development board (codenamed Bender).
On first two images you can see how Flextronics Semiconductor FPGA Development board is connect via JTAG and JP1 driver to a host PC. On third image Simon S. is using DDD to debug something running on the board.

Basic information about Flextronics FPGA Development board (PDF, 1.6MB). The board is not available as retail, but only to Flextronics clients doing a FPGA or an ASIC project together with Flextronics. For additional information about the board or the demo apps send an email to info@flextronics.si.

uClinux/OR32 Demo App on Xess XSV800

This demo uses uClinux 2.0.x port running pn OR1200 RISC processor. In order to run this demo, set your XSV800 board to 10 MHz (set frequency divisor to 10 with Xess utility GXSSETCLK). Since setting the frequency doesn't always work, check with an oscilloscope or similar tool that it is set properly. If you can't set it, consult Xess online documentation.
Download the linux-35.exo (4.4MB) file to onboard flash using GXSLOAD utility provided by Xess. Now you will also have to download a new CPLD configuration so that the Serial RS232 console will work. Download the cpld-tdm.svf (850KB) file. Connect the console terminal by attach a RS232 cable connected to a PC running some sort of terminal software (Minicom on Linux or HyperTerminal on Windows for example). Set communication parameters to 4800 baud, 8N1 (8 bits data, no parity, 1 stop bit). When the flash and CPLD are loaded, restart the board by turning power off and then back on. Now you should see something like this (can vary since uClinux port is under heavy development):

OpenRisc 1000 support (C) www.opencores.org

uClinux/OR32 on Xess XSV800
Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne
Calibrating delay loop.. ok - 0.81 BogoMIPS
Memory available: 1852k/2024k RAM, 0k/0k ROM (180k kernel data, 423k code)
Swansea University Computer Society NET3.035 for Linux 2.0
NET3: Unix domain sockets 0.13 for Linux NET3.035.
uClinux version 2.0.38.1pre3 (simons@odin) (gcc version 2.95.2 19991024 (release
)) #186 Mon Aug 6 20:45:43 CEST 2001
Serial driver version 4.13p1 with no serial options enabled
ttyS00 at 0x9c000000 (irq = 15) is a 16550A
Ramdisk driver initialized : 16 ramdisks of 512K size
Blkmem copyright 1998,1999 D. Jeff Dionne
Blkmem copyright 1998 Kenneth Albanowski
Blkmem 0 disk images:
RAMDISK: Romfs filesystem found at block 0
RAMDISK: Loading 385 blocks into ram disk... done.
VFS: Mounted root (romfs filesystem).
   request_irq irq = 15  IRQ_T(info) = 20000000
Executing sash

Sash command shell (version 1.1.1)
/>
/>
/> ls
Makefile
Makefile~
bin
dev
linuxrc
proc

/> date
Thu Jan 17 03:44:32 2002

/>

Ignore the BogoMIPS rating. Delay loop was not properly calibrated. We didn't try yet to increase speed of the processor. Looks like there is quite some margin left.

Non ORP demo app for Xess XSV800

This is an old demo app, available under OpenCores CVS hierarchy o1k/mp3. It is a MP3 demo that uses the OR1200 as the RISC processor running GNU GPLed version of the MP3 decoder software called MAD. In order to run this demo, set your XSV800 board to 20 MHz (set frequency divisor to 5 with Xess utility GXSSETCLK). Since setting the frequency doesn't always work, check with an oscilloscope or similar tool that it is set properly. If you can't set it, consult Xess online documentation. Attach a speaker or headsets to speaker out connector and download the classic.exo (3.3MB) file to onboard flash using GXSLOAD utility provided by Xess. When the flash is loaded, restart the board by turning power off and then back on. You should hear classical music. One switch button is used to position the player to the first song and and one to advance to the next song.

Mailing List / Discussion Forum / Page Maintainer

To participate in the development or simply to discuss ORPsoc issues and to report bugs, go to the openrisc mailing list. To subscribe to the list, follow mailing list subscribe instructions. This web page is maintained by Damjan Lampret.

Open Source Embedded Platform Based on OpenRISC and DE2-70

Xiang Li and Lin Zuo, master students of the SoC program of KTH, Sweden have developed a general purpose embedded platform which uses the OpenRISC OR1200 processor as the CPU. It is targeted to an ALTERA FPGA development board (Terasic's DE2-70). They have made a demo program which is able to decode a small MP3 file in PC, download the music data to the board via an Ethernet connection, and finally play the music on the board. For more details see www.olivercamel.com/post/master_thesis.html.

Models of ORPSoC

There is a high speed architectural model of ORPSoC. Details are on its own page, opencores.org/project,or1k,orpsoc. Icarus Verilog simulation models and Verilator cycle accurate SystemC models of ORPSoC are also available in CVS at or1k/orpsoc_models or as a compressed tar file for download at opencores.org/download.cgi?rjumpto=2zb.rat.0.1-sledom-cospro/k1ro/bew/igc.stcejorp.

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