Pipelined FFT/IFFT 128 points processor


Name: pipelined_fft_128
Created: Feb 1, 2010
Updated: Feb 2, 2010
SVN Updated: Feb 2, 2010
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Category:DSP core
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL


Pipelined FFT/IFFT 128 points IP core is a unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 128 – complex point FFT. The data and coefficient widths are adjustable in the range 8 to 16.

Main Features:

  • 128 -point radix-8 FFT
  • Forward and inverse FFT.
  • Pipelined mode operation, each result is outputted in one clock cycle, the latent delay from input to output is equal to 310 clock cycles (440 clock cycles when the direct output data order), simultaneous loading/downloading supported
  • Input data, output data, and coefficient widths are parametrizable in range 8 to 16
  • Two and three data buffers are selected.
  • FFT for 10 bit data and coefficient width is calculated on Xilinx XC4SX35-12 FPGA at 215 MHz clock cycle, and on Xilinx XC5VLX30-3 FPGA at 260 MHz clock cycle,respectively.
  • FFT unit for 10 bit data and coefficients, and 3 data buffers occupies 4147 CLB slices, 4 DSP48 blocks, and 5 kbit of RAM in Xilinx XC4SX35 FPGA, and 1254 CLB slices 4 DSP48E blocks, and 5 kbit of RAM in Xilinx XC5VLX30 FPGA.
  • Overflow detectors of intermediate and resulting data are present.
  • Two normalizing shifter stages provide the optimum data magnitude bandwidth.
  • Structure can be configured in Xilinx, Altera, Actel, Lattice FPGA devices, and ASIC.
  • Can be used in OFDM modems, software defined radio, multichannel coding.

Please, contact us if you wish to have this IP core modified or adjusted to meet your requirements.

This core is provided by Unicore Systems To view our product list of commercial IP cores, please, follow this link