Plasma - most MIPS I(TM) opcodes

Hello When I am trying to understand the code of plasma 32 bit core, I have found that the irq_status <= gpioA_in(31) & not gpioA_in(31) wich means that irq_status will have all the time '0'. Is it true?

irq_status <= gpioA_in(31) & not gpioA_in(31) & irq_eth_send & irq_eth_rec & counter_reg(18) & not counter_reg(18) & not uart_write_busy & uart_data_avail; Thanks.

I am not sure that I understand your questions. This line from plasma.vhd defines what each interrupt line into the Plasma CPU does. irq_status(0) is that data is available from the UART. irq_status(1) is that the UART write buffer is full.

irq_status <= gpioA_in(31) & not gpioA_in(31) & irq_eth_send & irq_eth_rec & counter_reg(18) & not counter_reg(18) & not uart_write_busy & uart_data_avail;

The file plasma.h has the same information:

/*** Interrupt bits **/ #define IRQ_UART_READ_AVAILABLE 0x01 #define IRQ_UART_WRITE_AVAILABLE 0x02 #define IRQ_COUNTER18_NOT 0x04 #define IRQ_COUNTER18 0x08 #define IRQ_ETHERNET_RECEIVE 0x10 #define IRQ_ETHERNET_TRANSMIT 0x20 #define IRQ_GPIO31_NOT 0x40 #define IRQ_GPIO31 0x80

Steve