Plasma - most MIPS I(TM) opcodes

hello Mr rhoads

I use your processor to describe an ASIP witch do morphological operations. But when examining your vhdl code I can not understand first why do you divise the clock by 2 knowing that the FPGA eval board contains a clock tree that gives you the desired frequency.Second, about the Mult bloc why it takes 32 cycles to achieve the division ? thank you

Hi, I think he did it, to use ddr sdram (double data rate) which operates in rising and falling edge. By dividing the clock, it would be easy to manipulate the memory.

Hi

the problem in fact is that I need to synthesis the ASIP based on the plasma at a frequency > 150Mhz, because I need to make comparison with other works witch achieved high frequencies, So when dividing the frequency this is really a big problem for me. I am not sure if I assign clk directly to clk_reg that will function correctly ?

If you aren't using the DDR controller, you should be able to change plasma_3e.vhd and set clk_reg directly as you have indicated.

If you need a higher clock speed consider changing mlite_cpu.vhd::pipeline_stages to 3.

The multiply and divide logic is a minimal size implementation. In mult.vhd there is C pseudo code for the multiply and divide algorithm.