Plasma - most MIPS I(TM) opcodes

1.In your control.vhd line 448, rs = "111111"; --interrupt vector, what's the function of interrupt vector? I checked interrupt vector(0x3c)'s data flow and found it ended in alu. It doesn't transfer to other modules any more. Then, how interrupt vector works? 2. In your reg_bank.vhd, you considered the situation when rs_index or rd_index are 101100. rs_index and rd_index come from control.vhd, but control.vhd doesn't output 101100 at all. Why you consider the situations when rs_index or rd_index are 101100?

I have known the answers of my questions. To understand the interrupt flow, we should read both VDHL and interrupt_service_routine in boot.asm. First, the hardware detects intr_signal and store PC in 101110(ram 00000). In the meantime, pc load interrupt vector address 0x0000003c. Second, in boot.asm, interrupt_service_routine is located in address 0x3c. then all registers are saved in memory. Third, jal OS_InterruptServiceRoutine, jump into interrupt function and then return. Fourth, restore all temporary registers Fifth, return to the pc before interrupt.

But, I don't understand 1. why line 86 "addi $5,$29,0". 2. In line 116
jr $26 mtc0 $27, $12 #STATUS=1; enable interrupts after jr $26, pc would be updated, how can mtc $27, $12 be executed?

Boot.asm line 86 copies the stack pointer to $5 which is the second argument to kernel/rtos.c::OS_InterruptServiceRoutine(uint32 status, uint32 *stack)

The Plasma CPU has a branch delay slot, so the instruction after a branch or jump is always executed before the CPU determines whether to take the branch or jump.

When control.vhd decodes COP0 opcodes, it sets the upper register address bit to a one. Therefore, if rs_index or rd_index most significant bit is set, then it is actually a COP0 register. When boot.asm::OS_AsmInterruptEnable executes "mfc0 $2, $12" or "mtc0 $4, $12" this will cause a reg_bank register address of 101100.