Plasma - most MIPS I(TM) opcodes

Hi, Rhoads In ddr_control.vhd, there is a state called STATE_POWER_ON. Does all the initialization in ddr_init.c run on this state? Once the initialization complete, state jumps to STATE_IDLE, right? Why we need to run MemoryRead(DDR_BASE) 100 times after the initialization ?

Thank you in advance.

another question: I think both Read and write need DQS signal. But, in your code, only when write_active is '1', DQS outputs high or low. How you provide DQS signals for a read cmd?

Does our ddr_ctrl support Random Read Accessed and Consecutive READ Bursts?

How often our DDR do auto-refresh? every 64/50M seconds? Many people think 64 ms is a good choice. But it seems that you didn't use 64ms, why?

The state STATE_POWER_ON is only exited after the first read at the end of DdrInit(). The read only happens once after a short delay.

I assume that you have read the DDR datasheet 512MBDDRx4x8x16.pdf. Regarding DQS from the datasheet: Data strobe: Output with read data, input with write data. DQS is edge aligned with read data, centered in write data. It is used to capture data.

ddr_ctrl supports random read or write accesses. It does not take advantage of faster consecutive read accesses. This make the cache even more important.

The refresh occurs if refresh_cnt(7) = '1' which will occur every 128 clock cycles. It needs 8192 cycles to fully refresh. 1/(25000000/128/8192) = 42ms.