Hi.

When using vsim, I encountered the following error:

Loading design_library.ram16x1d(ram16x1d_v)

** Fatal: (vsim-3420) Array lengths do not match. Left is 16 (15 downto 0). Right is 8 (0 to 7).

Time: 0 ps Iteration: 0 Instance: /tb/proc0/u4_reg_bank/xilinx_16x1d/reg_loop(0)/reg_bit1a File: unisims/primitive/RAM16X1D.vhd Line: 32

FATAL ERROR while loading design

Error loading design

Error loading design Command exited with non-zero status 12

The issue was solved changing the init value in RAM16X1D declaration in mlite_pack for 0x0016 instead of 0x16!

Hope it helps!

Thank you for reporting the problem.

In mlite_pack.vhd I changed:

component RAM16X1D generic (INIT : bit_vector := X"0000"); ... component RAM32X1D generic (INIT : bit_vector := X"00000000");