Potato Processor

Hi Skordal,

I would like to know if FENCE and FENCE.I is supported by potato and a brief description of how it works from a logical implementation perspective. I searched online but i`am not able to get much info on this or if you could suggest some resources that I could go through.

Tussen Takk !!

The fence instructions are currently treated as no-ops by the processor. In the near future, the fence.i instruction will be used to do a flush of the instruction cache.

The instructions are briefly described in the user-level RISC-V ISA documentation at <a href="http://riscv.org">http://riscv.org</a>.

The fence instructions are basically used to ensure that memory accesses initiated before the fence instruction are completed and their results visible to the processor before continuing. This is usually not a problem in the Potato processor, as all memory accesses are done in-order and the processor stalls until each access finishes before continuing, ensuring that the effects of each memory operation is visible to the next.

However, if a store operation modifies the instruction memory (for instance, when running self-modifying code), the instruction cache for the affected area will contain old data and need to be reloaded from memory. The fence.i instruction can be used to accomplish this, by flushing the instruction cache and thus "synchronizing the instruction and data streams" as the specification puts it.