Potato Processor

RISC-V Toolchain

In order to write applications for the Potato Processor, you need to have an updated RISC-V toolchain. To obtain such a toolchain, go to https://github.com/riscv/riscv-tools and follow the instructions to build and install the necessary tools.

Handling Interrupts

In addition to supporting the interrupts specified in the machine mode part of the RISC-V supervisor extensions, the Potato Processor also supports 8 IRQ inputs as interrupt sources.

To enable an interrupt, the corresponding bit has to be set in the mie register, where bits 24 to 31 correspond to IRQs 0 to 7. In addition, the master interrupt enable bit (bit 0) has to be set in the mstatus register as defined by the specification.

When handling an interrupt, the mip register can be used to check for pending IRQs. Just as in the mie register, bits 24 to 31 correspond to IRQs 0 to 7. Note that the bits in the mie register shows whether an interrupt is pending regardless of whether the interrupt is enabled in the mie register.

To determine which interrupt caused the interrupt handler to be run, the mcause register should be used. An IRQ interrupt causes the interrupt bit (bit 31) to be set and the interrupt number to be set to 16 plus the IRQ number.

To disable an interrupt, clear the corresponding bit in the mie register.

Caveats

There are some issues to keep in mind when programming for the Potato Processor:

• Unaligned memory accesses are not supported and will cause invalid address traps. To avoid this, make sure 32-bit reads and writes are done with 32-bit aligned addresses and that 16-bit reads and writes are done with 16-bit aligned addresses. Alternatively, a trap handler can be written to handle such cases.
• Hardware multiplication and division is not supported by the processor and must be handled in software. Attempting to use the hardware instructions for multiplication and division will cause undefined instruction traps.
• Unimplemented or unsupported CSRs do not cause invalid instruction traps, so take care to ensure that only M-mode CSRs are used in applications to prevent unintended behaviour.