Development of the Potato Processor has moved to GitHub, check it out on https://github.com/skordal/potato
The Potato Processor is a lightweight implementation of the RISC-V 32-bit integer ISA. It is implemented in VHDL, with a classic 5-stage RISC pipeline.
The processor datasheet can be downloaded here.
Notable features are:
The processor has been tested on a Nexys 4 board from Digilent. The design used for testing is included in the source distribution, with instructions on how to get it up and running.
An example design is included in the source distribution of the processor. Instructions on how to build and test this design is located in the example/ subdirectory of the Potato sources.