Project maintainers


Name: potato
Created: Apr 8, 2015
Updated: Nov 27, 2015
SVN Updated: Nov 14, 2015
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 9 reported / 7 solved
Star2you like it: star it!

Other project properties

Development status:Alpha
Additional info:Design done, FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: BSD

The Potato Processor

Development of the Potato Processor has moved to GitHub, check it out on

The Potato Processor is a lightweight implementation of the RISC-V 32-bit integer ISA. It is implemented in VHDL, with a classic 5-stage RISC pipeline.

The processor datasheet can be downloaded here.

Architectural Diagramme

Notable features are:

  • Supports the full RV32I subset of the RISC-V ISA, version 2.0.
  • Supports machine mode as defined by the RISC-V supervisor extensions, version 1.7.
  • Provides support for handling up to 8 IRQs without needing a separate interrupt controller.
  • Single-cycle execution of all instructions except memory load/store.
  • Includes a Wishbone compatible interface for integration into Wishbone-based systems.

The processor has been tested on a Nexys 4 board from Digilent. The design used for testing is included in the source distribution, with instructions on how to get it up and running.

Example Design

Example Application

An example design is included in the source distribution of the processor. Instructions on how to build and test this design is located in the example/ subdirectory of the Potato sources.