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Potato Processor

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doubt in privilege mode implementation #5
Closed akshayd opened this issue over 9 years ago
akshayd commented over 9 years ago

hello Skordal,

I have a quite basic doubt regarding the implementation of the privilege modes in RISC V ISA. The RISC V ISA has 4 modes viz. Machine, hypervisor, supervisor and User. Among these I plan to just work with Machine, Supervisor and User mode. Looking at the RISC V privilege ISA v1.7 it seems that the CSR address space is divided between the CSR from the 4 modes. So assuming Hypervisor is not to be implemented, how to implement the other 3 modes viz. machine,supervisor and user mode. Can I have 3 physical register sets belonging to the Machine, Supervisor and User mode each or I just need to have a Machine mode CSR implemnted in RTL and then need to add Supervisor and User mode registers.

Iam not able to figure out how to do this implementation in RTL. It will b really great if you could give me some idea about this.

Thanks a lot!!

skordal commented over 9 years ago
<p>Hi.</p><p> The Potato processor only supports the machine (M or Mbare) mode of the RISC-V privileged spec, in order to keep the processor simple. </p><p>If the other modes are required, it might be better to use the Rocket core from the RISC-V project (take a look <a href="http://riscv.org/download.html#tab_rocket">here</a> for details).</p><p>Kristian Skordal</p>
skordal closed this about 9 years ago
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