Potato Processor
Hi Skordal,
I have been going through the RISC V ISA and saw that there are different LOAD and STORE instructions based on the size of the data like LW,LB. while looking into potato I saw that the core checks the last 2 bits of the output of the alu to identify for data misalignment and then generates an appropriate exception corresponding to data width misalignment. My doubt is a check of the last 2 bit to 2'b00 can also be a valid data.
as per the below snippet
case mem_size is when MEMOP_SIZE_HALFWORD => if alu_result(0) /= '0' then data_misaligned <= '1'; else data_misaligned <= '0'; end if; when MEMOP_SIZE_WORD => if alu_result(1 downto 0) /= b"00" then data_misaligned <= '1'; else data_misaligned <= '0'; end if; when others => data_misaligned <= '0'; end case;
Also what is the rationale behind instruction misalignment check.
Hi.
<p> The data misalignment check looks at the two last bits of the address to determine if it is aligned correctly. The check looks at the result from the ALU since the load/store address is calculated by adding a register and a constant. </p><p> The reason for doing the misalignment checks, both for instruction and data addresses, is because the core itself does not support splitting up misaligned memory accesses into multiple bus accesses, as might be necessary. Raising an exception when an application attempts to do a misaligned access enables an application to manually do the misaligned access using two load or store instructions. </p>