Potato Processor

<p>Hi,</p><p>To detect misalignment in the data load/store instructions, the LSB bits of the ALU result is checked. This is because when executing a load or store instruction, the address to load from or store to is calculated by the ALU; therefore, if the ALU result is not a multiple of the data size you want to load or store, you have a misalignment.</p><p> If a data load/store exception occurs, the MEPC register will point to the instruction that caused the exception and the MBADADDR register will contain the invalid address that the instruction tried to access. </p><p> For instructions, the jump address is checked when executing branch or jump instructions. Since it is not possible to change the value of the PC without jump or branch instructions, the check is only required for these instructions. </p><p> If the PC is increased by 1 you will get an instruction misalignment exception. The invalid address will be stored in the MBADADDR register and the MEPC will point to the instruction that caused the exception. </p><p> PS: I am currently moving the project to GitHub, please post future issues on <a href="https://github.com/skordal/potato/issues">https://github.com/skordal/potato/issues</a> :-)</p> </p>