risc16f84
This page contains files uploaded to the old opencores website as well as images and documents intended for use on other pages in this project. If you want to download this project or browse its svn, you can do so at the overview-page.
| Date | File | Description |
| 2003-08-25 14:09 | risc16f84_clk2x.v | Cleaned up and revised edition, with interrupt support, and carry bit generation which corrects the mathematical error found recently. This same code is found in "b13c_environment.zip" |
| 2003-08-08 15:42 | b13c_environment.zip | Debugging environment, includes processor, serial debugger (with auto-BAUD), Xilinx BRAM blocks for memory and registers, simple LCD panel driver, single stepping logic, sample c-code program. |
| 2002-11-01 16:48 | risc16f84_small.v | Version without EEPROM interface and only 1 interrupt input. No auxiliary bus interface. 4 Clocks per instruction. |
| 2002-11-01 16:47 | risc16f84_lite.v | Version without EEPROM interface. 4 clocks per instruction. |
| 2002-11-01 16:46 | risc16f84.v | Full blown version. 4 clocks per instruction. Not tested in hardware. |
| 2002-05-09 00:37 | srec_to_rs232.pl | Perl script used to convert S-record files into a series of "rs232_syscon" commands. Used to load code into processor's memory one byte at a time! |
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