Clayton, John

risc16f84

You must provide a release with no internal tristate as some FPGA vendors does not allow internal tristate so not able to use the core.

SYNTHESIS: Can't synthetize. Unsolved tristate detected:

Untitled bug

Hi

I would like to use the clkx2 revision of the core, but I need the
timer0.

How can I introduce the timer0 in this revision?
Is so difficult?

Are hou thinking about wrinting this revision into hyerarchie sens?
I means into littles modules.

TIMER0

There seems to be a bug in the Int-State-Machine while restoring the PC after leaving the ISR. I can provide detaile information how to reproduce the bug. Pls. contact me.
/Tilman

ISR-Bug

Hello everybody !

I plan to use this core and I would like to know if anybody has already used it for real embedded application. Please let me know your experience about this core (bugs...)

Thanks in advance.

good core ?

When the op-code contains a litteral and this litteral is 0x03, it occurs that the wire "addr_stat" becomes true. In this particular case, an incorrect flag assignment occurs.

Add the following verilog code to patch this behavior : 

wire disable_status_z;
wire disable_status_c;
wire disable_status_dc;

// disable write access for status flags
assign disable_status_z  = (inst_addwf || inst_andwf || inst_clrf  || inst_clrw  || inst_comf  || inst_decf  || inst_incf  || inst_iorwf || inst_movf  || inst_subwf || inst_xorwf || inst_addlw || inst_andlw || inst_iorlw || inst_iorlw || inst_sublw || inst_xorlw) ? 1:0;

assign disable_status_c  = (inst_addwf || inst_subwf || inst_rlf   || inst_rrf   || inst_addlw || inst_sublw ) ? 1:0;

assign disable_status_dc = (inst_addwf || inst_subwf || inst_addlw || inst_sublw ) ? 1:0;

[...]

      // 2-5-2-2. Set data RAM/special registers,
      if (writeram_node)
      begin
        if (addr_stat)
        begin
          status_reg[7:5] <= aluout[7:5];      // write IRP,RP1,RP0
          // status(4),status(3)...unwritable, see below (/PD,/T0 part)

	      if( ~disable_status_c )
	          status_reg[0] <= aluout[0];      // write C
		  if( ~disable_status_dc )
	          status_reg[1] <= aluout[1];      // write DC
        end				    
        if (addr_fsr)        fsr_reg        <= aluout;       // write FSR
        if (addr_pclath)     pclath_reg     <= aluout[4:0];  // write PCLATH
        if (addr_intcon)     intcon_reg     <= aluout;       // write INTCON
        if (addr_aux_adr_lo) aux_adr_lo_reg <= aluout;       // write AUX low
        if (addr_aux_adr_hi) aux_adr_hi_reg <= aluout;       // write AUX high
      end

      // 2-5-2-3. Set/clear Z flag.
      if (addr_stat && ~disable_status_z) status_reg[2] <= aluout[2]; // (dest. is Z flag)
      else if (   inst_addlw || inst_addwf || inst_andlw || inst_andwf
               || inst_clrf  || inst_clrw  || inst_comf  || inst_decf
               || inst_incf  || inst_movf  || inst_sublw || inst_subwf
               || inst_xorlw || inst_xorwf || inst_iorlw || inst_iorwf )
              status_reg[2] <= aluout_zero_node; // Z=1 if result == 0

Incorrect flags assignment in STATUS special register

The interrupt condition was not correct. You must add "~next_exec_stall", otherwise the microcontroller will crash.

Original File:
    assign int_condition = (inte_sync_reg && ~exec_stall_reg && intcon_reg[7]);

Modified File:
    assign int_condition = (inte_sync_reg && ~exec_stall_reg && ~next_exec_stall && intcon_reg[7]);

Browse

risc16f84