Pipelined 32-bit RISC-V (RV32IM) Processor
Project maintainers
Details
Name: rv32im-pipelined
Created: Aug 29, 2026
Updated: Sep 1, 2026
SVN: No files checked in
Bugs: 0 reported / 0 solved
Created: Aug 29, 2026
Updated: Sep 1, 2026
SVN: No files checked in
Bugs: 0 reported / 0 solved
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Other project properties
Category:Processor
Language:Verilog
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
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The url of the svn repository is: https://opencores.org/websvn/listing/rv32im-pipelined/rv32im-pipelined
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