Description

5-stage pipelined 32-bit RISC-V RV32IM processor in Verilog (RV32I + M-extension for MUL/DIV).

Features: full data forwarding, load-use hazard detection, early branch resolution in ID, LB/LH/LBU/LHU/SB/SH/SW, JAL/JALR, iterative mul_div_unit. Memory: 4KB data SRAM (4x sky130_sram_1kbyte_1rw1r_8x1024_8 via OpenRAM) + 4KB instruction memory.

Verified: 16/16 SystemVerilog tests pass in Icarus Verilog (R-type, I-type, load-store, branches, forwarding, load-use stall, JAL/JALR, LUI/AUIPC, MUL/DIV incl. div-by-zero, x0, factorial, fibonacci, mixed stress).

Physical implementation: Yosys + OpenROAD with Sky130A PDK, 1.5mm2 (1250x1200um), 18,759 instances, 0 DRC. Non-Wishbone, single clock domain, no caches/CSRs/interrupts. RTL-to-GDS flow exploration, not tapeout-ready.

The url of the github repository is: https://github.com/rahul-shahtp/Pipelined-32-bit-RISCV-processor.git