Simple Asynchronous Serial Controller
Project maintainers
Details
Name: sasc
Created: Sep 17, 2002
Updated: Mar 30, 2006
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Sep 17, 2002
Updated: Mar 30, 2006
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star2you like it: star it!
Other project properties
Category:Communication controller
Language:Verilog
Development status:Stable
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License:
Language:Verilog
Development status:Stable
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License:
Description
Simple asynchronous serial controller (aka UART). Includes 4
byte receive and a 4 byte transmit FIFO (FIFO size can be easily
adjusted). External baud rate generator (included). Very small.
Features
- Implemented in Verilog
- Flow Control (CTS/RTS)
- 1 start bit, 1 stop bit, NO parity
- 4 byte receive FIFO
- 4 byte transmit FIFO
- Fully Synthesisable
- 102 LUTs in a Spartan II
Status
This core is fully functional and completed.
It was verified in hardware in an XESS XVC800 FPGA prototype
board with a Maxim RS232 line driver.
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