SAYEH educational processor
This page contains files uploaded to the old opencores website as well as images and documents intended for use on other pages in this project. If you want to download this project or browse its svn, you can do so at the overview-page.
| Date | File | Description |
| 2008-07-17 18:51 | SAYEH-U1-V.rar | Verilog description files of SAYEH processor and brief documentation about it's ISA. the controller module comes with 11 stage in this version. this version also implemented on Xilinx Spartan2 and Altra UP3 FPGA board. |
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