SAYEH educational processor
Project maintainers
Details
Created: May 30, 2008
Updated: Jul 17, 2008
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Other project properties
Language:Verilog
Development status:Stable
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
The SAYEH processor (Simple Architecture,Yet Enough Hardware) has been designed for educational and benchmarking purpose. Relying on the material of the computer architecture course provide the necessary background for understanding details of the hardware of SAYEH, so it could be useful IP core for graduate or last year undergraduate students to implement computer architecture materials in a real processor design.
Originally SAYEH has been developed in ECE at university of Tehran, IRAN.
Features
SAYEH has a register file that is used for data processing instructions, also has a 16-bit data bus, 16-bit address bus and 16-bit instruction set architecture with simple arithmetic ,logic and communicative instructions.
http://haghdoost.persiangig.com/sayeharchitecture.gif (SAYEH Architecture)
Status
- Latest version of Verilog description files uploaded.
- necessary information and documentation gathered from computer students in University of Tehran.