Hi,

I tried to run the testbench provided in the deliverable. However, it appears that the wishbone READ was not successful, with the ModelSim output attached below. It would be great to have some documentation on the testbench, as I found it fairly hard to figure out what went wrong in the testbench if the simulation prints out error messages.

access_to_reg TEST

Time: 13405

TEST 3.0: 0: Init Seq, No Response

*W, cycle already in progress when start_cycle routine was called! Time 13000

*W, cycle already in progress when start_cycle routine was called! Time 14000

*W, cycle already in progress when start_cycle routine was called! Time 14000

*W, cycle already in progress when start_cycle routine was called! Time 14000

*W, cycle already in progress when start_cycle routine was called! Time 14000

*W, cycle already in progress when start_cycle routine was called! Time 14000

*E, wb_block_read routine re-entered! Time 14000

Time: 14005

*E WISHBONE Master was unable to complete the requested read operation from MAC!

*W, cycle already in progress when start_cycle routine was called! Time 14000

*W, end_cycle routine called when CYC_O value was 0! Time 14000

*E, wb_block_read routine re-entered! Time 19000

Time: 19179

*E WISHBONE Master was unable to complete the requested read operation from MAC!

*W, cycle already in progress when start_cycle routine was called! Time 19000

*W, cycle already in progress when start_cycle routine was called! Time 19000

*E, wb_block_read routine re-entered! Time 19000

Time: 19387

*E WISHBONE Master was unable to complete the requested read operation from MAC!

*W, cycle already in progress when start_cycle routine was called! Time 19000

*W, cycle already in progress when start_cycle routine was called! Time 20000

*E, wb_block_read routine re-entered! Time 20000

Time: 19595

*E WISHBONE Master was unable to complete the requested read operation from MAC!

*E, wb_block_read routine re-entered! Time 20000

Time: 19621

*E WISHBONE Master was unable to complete the requested read operation from MAC!

*W, cycle already in progress when start_cycle routine was called! Time 20000

*W, cycle already in progress when start_cycle routine was called! Time 20000

*E, wb_block_read routine re-entered! Time 20000

Time: 19855

*E WISHBONE Master was unable to complete the requested read operation from MAC!

*E, wb_block_read routine re-entered! Time 20000

Time: 19881

*E WISHBONE Master was unable to complete the requested read operation from MAC!

CID reg 1: xxxxxxxx

*W, cycle already in progress when start_cycle routine was called! Time 20000

*W, cycle already in progress when start_cycle routine was called! Time 20000

*E, wb_block_read routine re-entered! Time 20000

Time: 20115

*E WISHBONE Master was unable to complete the requested read operation from MAC!

*E, wb_block_read routine re-entered! Time 20000

Time: 20141

*E WISHBONE Master was unable to complete the requested read operation from MAC!

RCA Response: xxxxxxxx

RCA Nr for data transfer: 0000xxxx

===========================================================================

T2 test_init_sequence Completed

===========================================================================

The test bench has been updated, if using modelsim please run the provide comp.do file.

If you still experience difficulties to run the core, please let me now